Browse this collection by:
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S. Rajagopal, "Data-parallel Digital Signal Processors: Algorithm Mapping, Architecture Scaling and Workload Adaptation," Ph.D. Thesis, 2004.
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S. Rajagopal, S. Rixner, J. R. Cavallaro and B. Aazhang, "DSP architectural considerations for optimal baseband processing," Texas Instruments TMS320 Educators Conference, 2002.
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S. Rajagopal, S. Bhashyam, J. R. Cavallaro and B. Aazhang,"Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers," in IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP),, pp. 173-184.
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S. Rajagopal, S. Bhashyam, J. R. Cavallaro and B. Aazhang, "Efficient VLSI architectures for multiuser channel estimation in wireless base-station receivers," Journal of VLSI Signal Processing, vol. 31, no. 2, pp. 143-156, 2002.
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S. Rajagopal, G. Xu and J. R. Cavallaro,"Implementation of Channel Estimation and Multiuser Detection Algorithms for W-CDMA on Digital Signal Processors," in Texas Instruments TMS320 Educators Conference,
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S. Rajagopal, S. Rixner and J. R. Cavallaro,"A programmable baseband processor design for software defined radios," in IEEE Midwest Conference on Circuits and Systems,, pp. 413-416.
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S. Rajagopal, S. Bhashyam, J. R. Cavallaro and B. Aazhang, "Real-Time Algorithms and Architectures for Multiuser Channel Estimation and Detection in Wireless Base-Station Receivers," IEEE Transactions on Wireless Communications, vol. 1, no. 3, pp. 468-489, 2002.
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B. A. Jones, S. Rajagopal and J. R. Cavallaro,"Real-Time DSP Multiprocessor Implementation for Future Wireless Base-Station Receivers," in Texas Instruments DSP Fest, Wireless Applications,
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S. Rajagopal, B. A. Jones and J. R. Cavallaro,"Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs," in International Conference on Signal Processing Applications and Technology (ICSPAT),
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S. Rajagopal and J. R. Cavallaro, "Truncated on-line arithmetic with applications to communication systems," IEEE Transactions on Computers, vol. 55, no. 10, pp. 1240-1252, 2006.
S. Rajagopal, "Data-parallel Digital Signal Processors: Algorithm Mapping, Architecture Scaling and Workload Adaptation," Ph.D. Thesis, 2004.
S. Rajagopal, S. Rixner, J. R. Cavallaro and B. Aazhang, "DSP architectural considerations for optimal baseband processing," Texas Instruments TMS320 Educators Conference, 2002.
S. Rajagopal, S. Bhashyam, J. R. Cavallaro and B. Aazhang,"Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers," in IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP),, pp. 173-184.
S. Rajagopal, S. Bhashyam, J. R. Cavallaro and B. Aazhang, "Efficient VLSI architectures for multiuser channel estimation in wireless base-station receivers," Journal of VLSI Signal Processing, vol. 31, no. 2, pp. 143-156, 2002.
S. Rajagopal, G. Xu and J. R. Cavallaro,"Implementation of Channel Estimation and Multiuser Detection Algorithms for W-CDMA on Digital Signal Processors," in Texas Instruments TMS320 Educators Conference,
S. Rajagopal, S. Rixner and J. R. Cavallaro,"A programmable baseband processor design for software defined radios," in IEEE Midwest Conference on Circuits and Systems,, pp. 413-416.
S. Rajagopal, S. Bhashyam, J. R. Cavallaro and B. Aazhang, "Real-Time Algorithms and Architectures for Multiuser Channel Estimation and Detection in Wireless Base-Station Receivers," IEEE Transactions on Wireless Communications, vol. 1, no. 3, pp. 468-489, 2002.
B. A. Jones, S. Rajagopal and J. R. Cavallaro,"Real-Time DSP Multiprocessor Implementation for Future Wireless Base-Station Receivers," in Texas Instruments DSP Fest, Wireless Applications,
S. Rajagopal, B. A. Jones and J. R. Cavallaro,"Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs," in International Conference on Signal Processing Applications and Technology (ICSPAT),
S. Rajagopal and J. R. Cavallaro, "Truncated on-line arithmetic with applications to communication systems," IEEE Transactions on Computers, vol. 55, no. 10, pp. 1240-1252, 2006.