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An Integrated CAD Framework Linking VLSI Layout Editors and Process Simulators

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Title: An Integrated CAD Framework Linking VLSI Layout Editors and Process Simulators
Author: Sengupta, Chaitali
Type: Masters Thesis
Keywords: Integrated CAD Framework; VLSI editors; process simulators
Citation: C. Sengupta, "An Integrated CAD Framework Linking VLSI Layout Editors and Process Simulators," Masters Thesis, pp. 102, 1995.
Abstract: This thesis presents an Integrated CAD Framework which links VLSI layout editors to lithographic simulators and provides information on the simulated resolution of a feature to the circuit designer. This will help designers to design more compact circuits, as they will be able to see the effect on manufactured silicon. The Framework identifies areas in a layout (in Magic or CIF format) that are more prone to problemsmask for a particular set of process parameters. The designer can modify the original layout based arising out of the photolithographic process. It then creates the corresponding in-puts for closer analysis with a process simulator (Depict) and analyzes the simulator outputs to decide whether the printed layout will match the designed upon this analysis. The Framework has been used to evaluate layouts for various process techniques. These evaluations illustrate the use of the Framework in determining the limits of any lithographic process.
Date Published: 1995-05-20

This item appears in the following Collection(s)

  • ECE Publications [1043 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications