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A Bandwidth-Efficient Architecture for Media Processing

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dc.contributor.author Rixner, Scott
Dally, William J.
Kapasi, Ujval J.
Khailany, Brucek
Lopez-Lagunas, Abelardo
Mattson, Peter
Owens, John D.
dc.creator Rixner, Scott
Dally, William J.
Kapasi, Ujval J.
Khailany, Brucek
Lopez-Lagunas, Abelardo
Mattson, Peter
Owens, John D.
dc.date.accessioned 2007-10-31T01:01:36Z
dc.date.available 2007-10-31T01:01:36Z
dc.date.issued 1998-11-20
dc.date.submitted 1998-11-20
dc.identifier.uri http://hdl.handle.net/1911/20277
dc.description Conference Paper
dc.description.abstract Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are poorly matched to conventional microprocessor architectures, they are a good fit for modern VLSI technology with its high arithmetic capacity but limited global bandwidth. The stream programming model, in which an application is coded as streams of data records passing through computation kernels, exposes both parallelism and locality in media applications that can be exploited by VLSI architectures. The Imagine architecture supports the stream programming model by providing a bandwidth hierarchy tailored to the demands of media applications. Compared to a conventional scalar processor, Imagine reduces the global register and memory bandwidth required by typical applications by factors of 13 and 21 respectively. This bandwidth efficiency enables a single chip Imagine processor to achieve a peak performance of 16.2GFLOPS (single-precision floating point) and sustained performance of up to 8.5GFLOPS on media processing kernels.
dc.language.iso eng
dc.subject media processing
stream processing
processor architecture
dc.title A Bandwidth-Efficient Architecture for Media Processing
dc.type Conference Paper
dc.date.note 2002-03-28
dc.citation.bibtexName inproceedings
dc.date.modified 2002-03-28
dc.subject.keyword media processing
stream processing
processor architecture
dc.citation.pageNumber 3-13
dc.citation.location Dallas, TX
dc.citation.conferenceName IEEE/ACM International Symposium on Microarchitecture (MICRO)
dc.type.dcmi Text
dc.identifier.citation S. Rixner, W. J. Dally, U. J. Kapasi, B. Khailany, A. Lopez-Lagunas, P. Mattson and J. D. Owens,"A Bandwidth-Efficient Architecture for Media Processing," in IEEE/ACM International Symposium on Microarchitecture (MICRO),, pp. 3-13.

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    Publications by Rice University Electrical and Computer Engineering faculty and graduate students