A Bandwidth-Efficient Architecture for Media Processing

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Title: A Bandwidth-Efficient Architecture for Media Processing
Author: Rixner, Scott; Dally, William J.; Kapasi, Ujval J.; Khailany, Brucek; Lopez-Lagunas, Abelardo; Mattson, Peter; Owens, John D.
Type: Conference Paper
Keywords: media processing; stream processing; processor architecture
Citation: S. Rixner, W. J. Dally, U. J. Kapasi, B. Khailany, A. Lopez-Lagunas, P. Mattson and J. D. Owens,"A Bandwidth-Efficient Architecture for Media Processing," in IEEE/ACM International Symposium on Microarchitecture (MICRO),, pp. 3-13.
Abstract: Media applications are characterized by large amounts of available parallelism, little data reuse, and a high computation to memory access ratio. While these characteristics are poorly matched to conventional microprocessor architectures, they are a good fit for modern VLSI technology with its high arithmetic capacity but limited global bandwidth. The stream programming model, in which an application is coded as streams of data records passing through computation kernels, exposes both parallelism and locality in media applications that can be exploited by VLSI architectures. The Imagine architecture supports the stream programming model by providing a bandwidth hierarchy tailored to the demands of media applications. Compared to a conventional scalar processor, Imagine reduces the global register and memory bandwidth required by typical applications by factors of 13 and 21 respectively. This bandwidth efficiency enables a single chip Imagine processor to achieve a peak performance of 16.2GFLOPS (single-precision floating point) and sustained performance of up to 8.5GFLOPS on media processing kernels.
Date Published: 1998-11-20

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    Publications by Rice University Electrical and Computer Engineering faculty and graduate students