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Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs

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Title: Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs
Author: Rajagopal, Sridhar; Jones, Bryan Allen; Cavallaro, Joseph R.
Type: Conference Paper
Keywords: multiprocessor; DSPs; FPGAs; receiver algorithms; task partitioning
Citation: S. Rajagopal, B. A. Jones and J. R. Cavallaro,"Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs," in International Conference on Signal Processing Applications and Technology (ICSPAT),
Abstract: This paper presents a multiprocessor solution to meet real-time requirements of implementing advanced algorithms for multiuser channel estimation and detection for third and fourth generation wireless base-station receivers. We identify the key bottlenecks in the algorithms and task-partition the algorithms on multiple processors. We get speedups, ranging from 1.19X to 5.92X for a dual-DSP implementation due to both additional computational power and additional internal memory compared to a single DSP implementation using external memory. We also identify parts of the algorithm that exhibit bit-level parallelism, not utilized by DSPs. FPGAs can then be used to accelerate these parts and meet real-time requirements of 128 Kbps for next generation wireless systems.
Date Published: 2000-10-20

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  • ECE Publications [1043 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications
  • DSP Publications [508 items]
    Publications by Rice Faculty and graduate students in digital signal processing.