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Title:
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Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs |
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Author:
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Rajagopal, Sridhar; Jones, Bryan Allen; Cavallaro, Joseph R.
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Type:
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Conference Paper |
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Keywords:
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multiprocessor; DSPs; FPGAs; receiver algorithms; task partitioning |
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Citation:
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S. Rajagopal, B. A. Jones and J. R. Cavallaro,"Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs," in International Conference on Signal Processing Applications and Technology (ICSPAT), |
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Abstract:
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This paper presents a multiprocessor solution to meet real-time requirements of implementing advanced algorithms for multiuser channel estimation and detection for third and fourth generation wireless base-station receivers. We identify the key bottlenecks in the algorithms and task-partition the algorithms on multiple processors. We get speedups, ranging from 1.19X to 5.92X for a dual-DSP implementation due to both additional computational power and additional internal memory compared to a single DSP implementation using external memory. We also identify parts of the algorithm that exhibit bit-level parallelism, not utilized by DSPs. FPGAs can then be used to accelerate these parts and meet real-time requirements of 128 Kbps for next generation wireless systems. |
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Date Published:
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2000-10-20 |
