deposit_your_work

Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers

Files in this item

Files Size Format View
Raj2000Jul5EfficientV.PDF 109.3Kb application/pdf Thumbnail
Raj2000Jul5EfficientV.PS 319.0Kb application/postscript View/Open

Show full item record

Item Metadata

Title: Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers
Author: Rajagopal, Sridhar; Bhashyam, Srikrishna; Cavallaro, Joseph R.; Aazhang, Behnaam
Type: Conference Paper
Keywords: VLSI architectures; baseband signal processing; wireless base-station receivers; DSP
Citation: S. Rajagopal, S. Bhashyam, J. R. Cavallaro and B. Aazhang,"Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers," in IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP),, pp. 173-184.
Abstract: A real-time VLSI architecture is designed for multiuser channel estimation, one of the core base-band processing operations in wireless base-station receivers. Future wireless basestation receivers will need to use sophisticated algorithms to support extremely high data rates and multimedia. Current DSP architectures are unable to fully exploit the parallelism and bit level arithmetic present in these algorithms. These features can be revealed and efficiently implemented by task partitioning the algorithms for a VLSI solution. We modify the channel estimation algorithm for a reduced complexity fixed-point hardware implementation. We show the complexity and hardware required for three different area-time tradeoffs: an area-constrained, a time-constrained and an area-time efficient architecture. The area-constrained architecture achieves low data rates with minimum hardware, which may be used in picocell base-stations. The time-constrained solution exploits the entire available parallelism and determines the maximum theoretical data rates. The area-time efficient architecture meets real-time requirements with minimum area overhead. The orders-of-magnitude difference between area and time constrained solutions reveals significant inherent parallelism in the algorithm. All proposed VLSI solutions exhibit better time performance than a previous DSP implementation.
Date Published: 2000-07-20

This item appears in the following Collection(s)

  • ECE Publications [1047 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • DSP Publications [508 items]
    Publications by Rice Faculty and graduate students in digital signal processing.
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications