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FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm

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dc.contributor.author Karkooti, Marjan
Cavallaro, Joseph R.
Dick, Chris
dc.creator Karkooti, Marjan
Cavallaro, Joseph R.
Dick, Chris
dc.date.accessioned 2007-10-31T00:49:07Z
dc.date.available 2007-10-31T00:49:07Z
dc.date.issued 2005-10-01
dc.date.submitted 2005-10-01
dc.identifier.uri http://hdl.handle.net/1911/20002
dc.description Conference Paper
dc.description.abstract This paper presents a novel architecture for matrix inversion by generalizing the QR decomposition-based recursive least square (RLS) algorithm. The use of Squared Givens rotations and a folded systolic array makes this architecture very suitable for FPGA implementation. Input is a 4 Ã 4 matrix of complex, floating point values. The matrix inversion design can achieve throughput of 0.13M updates per second on a state of the art Xilinx Virtex4 FPGA running at 115 MHz. Due to the modular partitioning and interfacing between multiple Boundary and Internal processing units, this architecture is easily extendable for other matrix sizes.
dc.subject QRD implementation
Squared Givens Rotation
dc.title FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm
dc.type Conference Paper
dc.date.note 2006-05-25
dc.citation.bibtexName inproceedings
dc.date.modified 2006-05-25
dc.contributor.center Center for Multimedia Communications (http://cmc.rice.edu/)
dc.subject.keyword QRD implementation
Squared Givens Rotation
dc.citation.pageNumber 1625 - 1629
dc.citation.conferenceName Asilomar Conference on Signals, Systems, and Computers
dc.identifier.citation M. Karkooti, J. R. Cavallaro and C. Dick,"FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm," in Asilomar Conference on Signals, Systems, and Computers,, pp. 1625 - 1629.
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  • ECE Publications [1028 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [272 items]
    Publications by Rice Faculty and graduate students in multimedia communications