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FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm

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Title: FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm
Author: Karkooti, Marjan; Cavallaro, Joseph R.; Dick, Chris
Type: Conference paper
Keywords: QRD implementation; Squared Givens Rotation
Citation: M. Karkooti, J. R. Cavallaro and C. Dick, "FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm," pp. 1625 - 1629, 2005.
Abstract: This paper presents a novel architecture for matrix inversion by generalizing the QR decomposition-based recursive least square (RLS) algorithm. The use of Squared Givens rotations and a folded systolic array makes this architecture very suitable for FPGA implementation. Input is a 4 Ã 4 matrix of complex, floating point values. The matrix inversion design can achieve throughput of 0.13M updates per second on a state of the art Xilinx Virtex4 FPGA running at 115 MHz. Due to the modular partitioning and interfacing between multiple Boundary and Internal processing units, this architecture is easily extendable for other matrix sizes.
Date Published: 2005-10-01

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  • ECE Publications [1048 items]
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    Publications by Rice Faculty and graduate students in multimedia communications