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Semi-Parallel Architectures For Real-time LDPC Coding

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dc.contributor.author Karkooti, Marjan
dc.creator Karkooti, Marjan
dc.date.accessioned 2007-10-31T00:49:02Z
dc.date.available 2007-10-31T00:49:02Z
dc.date.issued 2004-05-01
dc.date.submitted 2004-05-06
dc.identifier.uri http://hdl.handle.net/1911/20000
dc.description Masters Thesis
dc.description.abstract Error correcting codes (ECC) enable the communication systems to have a low-power, reliable transmission over noisy channels. ow Density Parity Check codes are the best known ECC code that can achieve data rates very close to Shannon limit. This thesis presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used for the decoder, which has the advantage of simpler computations compared to Sum-Product algorithm without any loss in performance. To balance the area-time trade-off of the design, a special structure is proposed for the parity-check matrix. An efficient semi-parallel decoder for a family of (3,6) LDPC codes has been implemented in VHDL for programmable hardware. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps. The design is scalable and reconfigurable for different block sizes.
dc.description.sponsorship Nokia
dc.description.sponsorship Nokia/Texas Instruments
dc.description.sponsorship National Instruments
dc.subject Reconfigurable architecture
FPGA implementation
channel coding
parallel architecture
area-time tradeoffs.
dc.title Semi-Parallel Architectures For Real-time LDPC Coding
dc.type Masters Thesis
dc.citation.bibtexName mastersthesis
dc.citation.journalTitle Masters Thesis
dc.date.modified 2004-08-30
dc.contributor.center Center for Multimedia Communications (http://cmc.rice.edu/)
dc.subject.keyword Reconfigurable architecture
FPGA implementation
channel coding
parallel architecture
area-time tradeoffs.
dc.citation.location Houston, TX
dc.identifier.citation M. Karkooti, "Semi-Parallel Architectures For Real-time LDPC Coding," Masters Thesis, 2004.
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  • ECE Publications [1029 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [272 items]
    Publications by Rice Faculty and graduate students in multimedia communications