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CAPE - VLSI Implementation of a Systolic Processor Array: Architecture, Design and Testing

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dc.contributor.author Hemkumar, Nariankadu D.
Kota, Kishore
Cavallaro, Joseph R.
dc.creator Hemkumar, Nariankadu D.
Kota, Kishore
Cavallaro, Joseph R.
dc.date.accessioned 2007-10-31T00:46:34Z
dc.date.available 2007-10-31T00:46:34Z
dc.date.issued 1991-06-20
dc.date.submitted 1991-06-20
dc.identifier.uri http://hdl.handle.net/1911/19944
dc.description Conference Paper
dc.description.abstract The SVD is an important matrix decomposition in many real-time signal processing, image processing and robotics applications. Special-purpose processor arrays can achieve significant speed-up over conventioinal architectures through the use of efficient parallel algorithms. The Cordic Array Processor Element (CAPE) is a single chip VLSI implementation of a processor element for the Brent-Luk-VanLoan systolic array which computes the SVD of a real matrix. The array utilizes CORDIC (Co-ordinate Rotation Digital Computer) arithmetic to perform the vector rotations and inverse tangent calculations in hardware. A six-chip prototype of the processor has been implemented as TinyChips using the MOSIS fabricatioin service. Experience gained from designing the prototype helped in the design of integrated single chip version. The chip has been implemented on a 5600 x 6900ì die in a 2ì n-well scalable CMOS process.
dc.subject Cordic Array Processor Element (CAPE)
VLSI implementation
systolic processor array
CORDIC (Co-ordinate Rotation Digital Computer)
SVD
matrix
dc.title CAPE - VLSI Implementation of a Systolic Processor Array: Architecture, Design and Testing
dc.type Conference Paper
dc.date.note 2001-08-28
dc.citation.bibtexName inproceedings
dc.date.modified 2001-08-28
dc.contributor.center Center for Multimedia Communications (http://cmc.rice.edu/)
dc.subject.keyword Cordic Array Processor Element (CAPE)
VLSI implementation
systolic processor array
CORDIC (Co-ordinate Rotation Digital Computer)
SVD
matrix
dc.citation.pageNumber 64-69
dc.citation.location Melbourne, FL
dc.citation.conferenceName University/Government/Industry Microelectronics Symposium
dc.identifier.citation N. D. Hemkumar, K. Kota and J. R. Cavallaro,"CAPE - VLSI Implementation of a Systolic Processor Array: Architecture, Design and Testing," in University/Government/Industry Microelectronics Symposium,, pp. 64-69.

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    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • DSP Publications [508 items]
    Publications by Rice Faculty and graduate students in digital signal processing.