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CAPE - VLSI Implementation of a Systolic Processor Array: Architecture, Design and Testing

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Title: CAPE - VLSI Implementation of a Systolic Processor Array: Architecture, Design and Testing
Author: Hemkumar, Nariankadu D.; Kota, Kishore; Cavallaro, Joseph R.
Type: Conference Paper
Keywords: Cordic Array Processor Element (CAPE); VLSI implementation; systolic processor array; CORDIC (Co-ordinate Rotation Digital Computer); SVD; matrix
Citation: N. D. Hemkumar, K. Kota and J. R. Cavallaro,"CAPE - VLSI Implementation of a Systolic Processor Array: Architecture, Design and Testing," in University/Government/Industry Microelectronics Symposium,, pp. 64-69.
Abstract: The SVD is an important matrix decomposition in many real-time signal processing, image processing and robotics applications. Special-purpose processor arrays can achieve significant speed-up over conventioinal architectures through the use of efficient parallel algorithms. The Cordic Array Processor Element (CAPE) is a single chip VLSI implementation of a processor element for the Brent-Luk-VanLoan systolic array which computes the SVD of a real matrix. The array utilizes CORDIC (Co-ordinate Rotation Digital Computer) arithmetic to perform the vector rotations and inverse tangent calculations in hardware. A six-chip prototype of the processor has been implemented as TinyChips using the MOSIS fabricatioin service. Experience gained from designing the prototype helped in the design of integrated single chip version. The chip has been implemented on a 5600 x 6900ì die in a 2ì n-well scalable CMOS process.
Date Published: 1991-06-20

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  • ECE Publications [1032 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • DSP Publications [508 items]
    Publications by Rice Faculty and graduate students in digital signal processing.