|
Title:
|
Low Power VLSI Architecture for Adaptive MAI Suppression in CDMA Using Multi-stage Convergence Masking Vector |
|
Author:
|
Guo, Yuanbin; McCain, Dennis; Cavallaro, Joseph R.
|
|
Type:
|
Conference Paper |
|
Keywords:
|
SoC architecture; low power; adaptive; MAI |
|
Citation:
|
Y. Guo, D. McCain and J. R. Cavallaro,"Low Power VLSI Architecture for Adaptive MAI Suppression in CDMA Using Multi-stage Convergence Masking Vector," in IEEE Vehicular Technology Conference (VTC), |
|
Abstract:
|
In this paper, we propose a novel low power and low complexity multi-stage Parallel-Residue-Compensation (PRC) architecture for enhanced MAI suppression in the CDMA systems. The accuracy of the interference cancellation is improved with a set of weights computed from an adaptive Normalized Least-Mean-Square (NLMS) algorithm. The physical meaning of the complete versus weighted interference cancellation is applied to clip the weights above a certain threshold. Multistage Convergence-Masking-Vector (CMV) is then proposed to combine with the clock gating as a dynamic power management scheme in the VLSI receiver architecture. This reduces the dynamic power consumption in the VLSI architecture by up to 90% with a negligible performance loss. |
|
Date Published:
|
2005-09-01 |
