deposit_your_work

Low Power VLSI Architecture for Adaptive MAI Suppression in CDMA Using Multi-stage Convergence Masking Vector

Files in this item

Files Size Format View
Guo2005Sep5LowPowerVL.PDF 169.3Kb application/pdf Thumbnail

Show full item record

Item Metadata

Title: Low Power VLSI Architecture for Adaptive MAI Suppression in CDMA Using Multi-stage Convergence Masking Vector
Author: Guo, Yuanbin; McCain, Dennis; Cavallaro, Joseph R.
Type: Conference paper
Keywords: SoC architecture; low power; adaptive; MAI
Citation: Y. Guo, D. McCain and J. R. Cavallaro, "Low Power VLSI Architecture for Adaptive MAI Suppression in CDMA Using Multi-stage Convergence Masking Vector," 2005.
Abstract: In this paper, we propose a novel low power and low complexity multi-stage Parallel-Residue-Compensation (PRC) architecture for enhanced MAI suppression in the CDMA systems. The accuracy of the interference cancellation is improved with a set of weights computed from an adaptive Normalized Least-Mean-Square (NLMS) algorithm. The physical meaning of the complete versus weighted interference cancellation is applied to clip the weights above a certain threshold. Multistage Convergence-Masking-Vector (CMV) is then proposed to combine with the clock gating as a dynamic power management scheme in the VLSI receiver architecture. This reduces the dynamic power consumption in the VLSI architecture by up to 90% with a negligible performance loss.
Date Published: 2005-09-01

This item appears in the following Collection(s)

  • ECE Publications [1048 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications