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FFT-Accelerated Iterative MIMO Chip Equalizer Architecture For CDMA Downlink

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Title: FFT-Accelerated Iterative MIMO Chip Equalizer Architecture For CDMA Downlink
Author: Guo, Yuanbin; McCain, Dennis; Cavallaro, Joseph R.
Type: Conference Paper
Keywords: MIMO; chip equalizer; CDMA; iterative
Citation: Y. Guo, D. McCain and J. R. Cavallaro,"FFT-Accelerated Iterative MIMO Chip Equalizer Architecture For CDMA Downlink," in IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP),
Abstract: In this paper, we present a novel FFT-accelerated iterative Linear MMSE chip equalizer in the MIMO CDMA downlink receiver. The reversed form time-domain matrix multiplication in the Conjugate Gradient iteration is accelerated by an equivalent frequency-domain circular convolution with FFT-based "overlap-save" architecture. The iteration rapidly refines a crude initial approximation to the actual final equalizer taps. This avoids the Direct-Matrix-Inverse with O((NL)³) complexity, and reduces the standard CG complexity from O((NL)²) to O(NLlog2(NL)). Simulation demonstrates strong numerical stability and promising performance/complexity tradeoff, especially for very long channels.
Date Published: 2005-03-01

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