deposit_your_work

An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture

Files in this item

Files Size Format View
Guo2005Dec1AnEfficien.PDF 420.6Kb application/pdf Thumbnail

Show full item record

Item Metadata

Title: An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture
Author: Guo, Yuanbin; Zhang, Jianzhong (Charlie); McCain, Dennis; Cavallaro, Joseph R.
Type: Journal Paper
Keywords: MIMO equalizer; circulant; VLSI
Citation: Y. Guo, J. (. Zhang, D. McCain and J. R. Cavallaro, "An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture," EURASIP Journal on Applied Signal Processing, 2005.
Abstract: In this paper, we present an efficient circulant approximation based MIMO equalizer architecture for the CDMA downlink. This reduces the Direct-Matrix-Inverse (DMI) of size (NF x NF) with O((NF)&sup3;) complexity to some FFT operations with O(NF log<sub>2</sub>(F)) complexity and the inverse of some (N x N) sub-matrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the (4 x 4) high-order receiver from partitioned (2 x 2) sub-matrices. This leads to more parallel VLSI design with 3x further complexity reduction. Comparative study with both the Conjugate-Gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C High-Level-Synthesis methodology.
Date Published: 2005-12-01

This item appears in the following Collection(s)

  • ECE Publications [1046 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications