deposit_your_work

Low Complexity System-On-Chip Architectures Of Optimal Parallel-Residue-Compensation In CDMA Systems

Files in this item

Files Size Format View
Guo2004Jun5LowComple.PDF 279.4Kb application/pdf Thumbnail

Show full item record

Item Metadata

Title: Low Complexity System-On-Chip Architectures Of Optimal Parallel-Residue-Compensation In CDMA Systems
Author: Guo, Yuanbin; McCain, Dennis; Cavallaro, Joseph R.
Type: Conference Paper
Keywords: System-On-Chip; Parallel-Residue-Compensation; Interference Cancellation; CDMA
Citation: Y. Guo, D. McCain and J. R. Cavallaro,"Low Complexity System-On-Chip Architectures Of Optimal Parallel-Residue-Compensation In CDMA Systems," in IEEE International Symposium on Circuits and Systems (ISCAS),, pp. 77-80.
Abstract: In this paper, we propose a novel multi-stage Parallel-Residue-Compensation (PRC) receiver architecture for enhanced suppression of the MAI in CDMA systems. We extract the commonality to avoid the direct Interference Cancellation and reduce the algorithm complexity from O(K²N) to O(KN). In the second part, scalable VLSI architectures are implemented in a FPGA prototyping system with an efficient Precision-C System-on-Chip (SOC) design methodology. Hardware efficiency is achieved by investigating multi-level parallelism and pipelines. The design of Sum-Sub-MUX Unit (SMU) combinational logic avoids the usage of dedicated multipliers with at least 10X saving in hardware resources. The most area/timing efficient design only uses area similar to the most area constraint architecture but gives at least 4X speedup over a conventional design.
Date Published: 2004-05-01

This item appears in the following Collection(s)

  • ECE Publications [1046 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications