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Title:
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Low Complexity System-On-Chip Architectures Of Optimal Parallel-Residue-Compensation In CDMA Systems |
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Author:
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Guo, Yuanbin; McCain, Dennis; Cavallaro, Joseph R.
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Type:
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Conference Paper |
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Keywords:
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System-On-Chip; Parallel-Residue-Compensation; Interference Cancellation; CDMA |
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Citation:
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Y. Guo, D. McCain and J. R. Cavallaro,"Low Complexity System-On-Chip Architectures Of Optimal Parallel-Residue-Compensation In CDMA Systems," in IEEE International Symposium on Circuits and Systems (ISCAS),, pp. 77-80. |
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Abstract:
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In this paper, we propose a novel multi-stage Parallel-Residue-Compensation (PRC) receiver architecture for enhanced suppression of the MAI in CDMA systems. We extract the commonality to avoid the direct Interference Cancellation and reduce the algorithm complexity from O(K²N) to O(KN). In the second part, scalable VLSI architectures are implemented in a FPGA prototyping system with an efficient Precision-C System-on-Chip (SOC) design methodology. Hardware efficiency is achieved by investigating multi-level parallelism and pipelines. The design of Sum-Sub-MUX Unit (SMU) combinational logic avoids the usage of dedicated multipliers with at least 10X saving in hardware resources. The most area/timing efficient design only uses area similar to the most area constraint architecture but gives at least 4X speedup over a conventional design. |
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Date Published:
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2004-05-01 |
