deposit_your_work

Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink

Files in this item

Files Size Format View
Guo2003Nov5ScalableF.PDF 281.8Kb application/pdf Thumbnail

Show full item record

Item Metadata

Title: Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink
Author: Guo, Yuanbin; McCain, Dennis; Zhang, Jianzhong (Charlie); Cavallaro, Joseph R.
Type: Conference Paper
Keywords: FPGA; chip equalizer; SIMO; HSDPA
Publisher: IEEE
Citation: Y. Guo, D. McCain, J. (. Zhang and J. R. Cavallaro,"Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink," in Asilomar Conference on Signals, Systems, and Computers,, pp. 2171 - 2175.
Abstract: In this paper, scalable FPGA architectures for the LMMSE-based chip-level equalizer in HSDPA downlink re-ceivers are studied. An FFT-based algorithm is applied to avoid the direct matrix inverse by utilizing the block-Toeplitz structure of the correlation matrix. A Pipelined-Multiplexing-Scheduler (PMS) is designed in the front-end to achieve scalable computation of the correlation coefficients. Very efficient VLSI architectures are designed by investigat-ing the multiple level parallelism and pipelining with a Precision-C based High-Level-Synthesis (HLS) design methodology. A 1Ã 2 Single-Input-Multiple-Output (SIMO) downlink receiver is designed and integrated in the HSDPA prototype system with Xilinx Virtex-II XC2V6000 FPGAs. The design demonstrates more area/time efficiency by achieving the best tradeoffs between the usage of functional units and real-time requirements.
Date Published: 2003-11-01

This item appears in the following Collection(s)

  • ECE Publications [1034 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students