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ASIP Architecture for Future Wireless Systems: Flexibility and Customization

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Title: ASIP Architecture for Future Wireless Systems: Flexibility and Customization
Author: Cavallaro, Joseph R.; Radosavljevic, Predrag
Type: Conference Paper
Keywords: ASIP; 3GPP; ASIC; DSP; Flexibility; Customization; Retargetable Compiler; Hardware Design Flow
Citation: J. R. Cavallaro and P. Radosavljevic,"ASIP Architecture for Future Wireless Systems: Flexibility and Customization," in Wireless World Research Forum (WWRF),
Abstract: Efficiency and flexibility are crucial features of the processors in the next generation of wireless cellular systems. Processors need to be efficient in order to satisfy real-time requirements for very demanding algorithms in new emerging wireless standards (3GPP, 4G, 802.11x, WiFi, DVD-S2, DAB, just to name a few). Flexibility, on the other hand, allows design modifications to respond to the evolution of standards (from GPRS to 3G, for example), worldwide compatibility (UMTS in Europe and Asia, CDMA2000 in North America), changes of user requirements depending of the quality of service (QoS), etc. Often, efficiency and flexibility goals are conflicting. Efficiency is related to the more custom hardware implementation such as ASIC processors. On the other hand, flexibility is the basic feature of programmable platforms such as DSP processors. While computationally efficient and low power solutions, ASIC processors for wireless applications are often not flexible enough to support necessary variations of implemented algorithms. ASIC design, especially in deep sub micron technologies, is very complex task and the manufacturing costs are also high. It is cheaper to write and debug software (application written in high level languages) than directly design, debug and manufacture hardware. Furthermore, there are increasing demands for products with low time-to-market, which is not primary characteristic of the ASIC design. On the other hand, DSP processor, although fully programmable, cannot achieve high performance with low power dissipation. DSP cores are often not able to achieve high level of instruction and data parallelism required for future generations of wireless systems.
Date Published: 2004-06-01

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  • ECE Publications [1032 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • DSP Publications [508 items]
    Publications by Rice Faculty and graduate students in digital signal processing.