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Exploiting instruction-level parallelism for memory system performance

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dc.contributor.advisor Adve, Sarita
dc.creator Pai, Vijay Sadananda
dc.date.accessioned 2009-06-04T08:26:38Z
dc.date.available 2009-06-04T08:26:38Z
dc.date.issued 2000
dc.identifier.uri http://hdl.handle.net/1911/18009
dc.description.abstract Current microprocessors improve performance by exploiting instruction-level parallelism (ILP). ILP hardware techniques such as multiple instruction issue, out-of-order (dynamic) issue, and non-blocking reads can accelerate both computation and data memory references. Since computation speeds have been improving faster than data memory access times, memory system performance is quickly becoming the primary obstacle to achieving high performance. This dissertation focuses on exploiting ILP techniques to improve memory system performance. This dissertation includes both an analysis of ILP memory system performance and optimizations developed using the insights of this analysis. First, this dissertation shows that ILP hardware techniques, used in isolation, are often unsuccessful at improving memory system performance because they fail to extract parallelism among data reads that miss in the processor's caches. The previously-studied latency-tolerance technique of software prefetching provides some improvement by initiating data read misses earlier, but also suffers from limitations caused by exposed startup latencies, excessive fetch-ahead distances, and references that are hard to prefetch. This dissertation then uses the above insights to develop compile-time software transformations that improve memory system parallelism and performance. These transformations improve the effectiveness of ILP hardware, reducing exposed latency by over 80% for a latency-detection microbenchmark and reducing execution time an average of 25% across 14 multiprocessor and uniprocessor cases studied in simulation and an average of 21% across 12 cases on a real system. These transformations also combine with software prefetching to address key limitations in either latency-tolerance technique alone, providing the best performance when both techniques are combined for most of the uniprocessor and multiprocessor codes that we study. Finally, this dissertation also explores appropriate evaluation methodologies for ILP shared-memory multiprocessors. Memory system parallelism is a key feature determining ILP performance, but is neglected in previous-generation fast simulators. This dissertation highlights the errors possible in such simulators and presents new evaluation methodologies to improve the tradeoff between accuracy and evaluation speed.
dc.format.extent 139 p.
dc.format.mimetype application/pdf
dc.language.iso eng
dc.subject Engineering, Electronics and Electrical
Computer Science
dc.title Exploiting instruction-level parallelism for memory system performance
dc.type.genre Thesis
dc.type.material Text
thesis.degree.discipline Engineering
thesis.degree.discipline Computer Science
thesis.degree.grantor Rice University
thesis.degree.level Doctoral
thesis.degree.name Doctor of Philosophy
dc.identifier.citation Pai, Vijay Sadananda. (2000) "Exploiting instruction-level parallelism for memory system performance." Doctoral Thesis, Rice University. http://hdl.handle.net/1911/18009.

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