deposit_your_work

Semi-parallel architectures for real-time LDPC coding

Files in this item

Files Size Format View
1419094.PDF 2.903Mb application/pdf Thumbnail

Show full item record

Item Metadata

Title: Semi-parallel architectures for real-time LDPC coding
Author: Karkooti, Marjan
Advisor: Cavallaro, Joseph R.
Degree: Master of Science thesis
Abstract: Error correcting codes (ECC) enable the communication systems to have a low-power, reliable transmission over noisy channels. Low Density Parity Check codes are the best known ECC code that can achieve data rates very close to Shannon limit. This thesis presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used for the decoder, which has the advantage of simpler computations compared to Sum-Product algorithm without any loss in performance. To balance the area time trade-off of the design, a special structure is proposed for the parity-check matrix. An efficient semi-parallel decoder for a family of (3, 6) LDPC codes has been implemented in VHDL for programmable hardware. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps. The design is scalable and reconfigurable for different block sizes.
Citation: Karkooti, Marjan. (2004) "Semi-parallel architectures for real-time LDPC coding." Masters Thesis, Rice University. http://hdl.handle.net/1911/17694.
URI: http://hdl.handle.net/1911/17694
Date: 2004

This item appears in the following Collection(s)