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The design of a scalable, hierarchical-bus, shared-memory multiprocessor

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Title: The design of a scalable, hierarchical-bus, shared-memory multiprocessor
Author: Greenwood, Jay Alan
Advisor: Bennett, John K.
Abstract: The hierarchical-bus architecture is an attractive solution to many of the problems associated with connecting processors together into a multiprocessing system but it also poses a number of design challenges. This thesis evaluates several architectural features of a hierarchical-bus multiprocessor. Our results show that applications with significant amounts of shared data achieve higher performance when run on a multiprocessor with a hierarchy of buses than on a single-bus multiprocessor. Also, applications with a significant number of write accesses to private data perform better using a cache protocol that modifies data within the cache (a copy-back protocol). This thesis describes a copy-back protocol for a hierarchical-bus multiprocessor and compares it with a cache protocol that broadcasts writes on the bus (a write-through protocol).
Citation: Greenwood, Jay Alan. (1992) "The design of a scalable, hierarchical-bus, shared-memory multiprocessor." Masters Thesis, Rice University. http://hdl.handle.net/1911/13618.
URI: http://hdl.handle.net/1911/13618
Date: 1992

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