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Architectural, numerical and implementation issues in the VLSI design of an integrated CORDIC-SVD processor

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Title: Architectural, numerical and implementation issues in the VLSI design of an integrated CORDIC-SVD processor
Author: Kota, Kishore
Advisor: Cavallaro, Joseph R.
Abstract: This thesis describes the design of a systolic array for computing the Singular Value Decomposition (SVD) based on the Brent, Luk, Van Loan array. The use of COordinate Rotation DIgital Computer (CORDIC) arithmetic results in an efficient VLSI implementation of the processor that forms the basic unit of the array. A six-chip custom VLSI chip set for the processor was initially designed, fabricated in a 2.0$\mu$ CMOS n-well process, and tested. The CORDIC Array Process Element (CAPE), a single chip implementation, incorporates several enhancements based on a detailed error analysis of fixed-point CORDIC. The analysis indicates a need to normalize input values for inverse tangent computations. This scheme was implemented using a novel method that has $O(n\sp{1.5})$ hardware complexity. Use of previous techniques to implement such a normalization would require $O(n\sp2)$ hardware. Enhanced architectures, which reduce idle time in the array either through pipelining or by improving on a broadcast technique, are also presented.
Citation: Kota, Kishore. (1991) "Architectural, numerical and implementation issues in the VLSI design of an integrated CORDIC-SVD processor." Masters Thesis, Rice University. http://hdl.handle.net/1911/13529.
URI: http://hdl.handle.net/1911/13529
Date: 1991

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