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S. Rajagopal, "Baseband Architecture Design for Future Wireless Base-Station Receivers," Masters Thesis, 2000.
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S. Rajagopal, S. Bhashyam, J. R. Cavallaro and B. Aazhang,"Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers," in IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP),, pp. 173-184.
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B. A. Jones, S. Rajagopal and J. R. Cavallaro,"Real-Time DSP Multiprocessor Implementation for Future Wireless Base-Station Receivers," in Texas Instruments DSP Fest, Wireless Applications,
S. Rajagopal, "Baseband Architecture Design for Future Wireless Base-Station Receivers," Masters Thesis, 2000.
S. Rajagopal, S. Bhashyam, J. R. Cavallaro and B. Aazhang,"Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers," in IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP),, pp. 173-184.
B. A. Jones, S. Rajagopal and J. R. Cavallaro,"Real-Time DSP Multiprocessor Implementation for Future Wireless Base-Station Receivers," in Texas Instruments DSP Fest, Wireless Applications,