Browse this collection by:
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V. S. Pai, S. Rixner and H. Kim, "Isolating the Performance Impacts of Network Interface Cards through Microbenchmarks," Rice University ECE Technical Report, no. EE0401, 2004.
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K. Skadron, M. Martonosi, D. August, M. Hill, D. Lilja and V. S. Pai, "Challenges in Computer Architecture Evaluation," IEEE Computer, vol. 36, no. 8, pp. 30-36, 2003.
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H. Kim, V. S. Pai and S. Rixner,"Exploiting Task-Level Concurrency in a Programmable Network Interface," in ACM SIGPLAN Symposium on Principles and Practices of Parallel Programming (PPoPP),
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V. S. Pai, A. Cox, V. S. Pai and W. Zwaenepoel,"A Flexible and Efficient Application Programming Interface (API) for a Customizable Proxy Cache," in USENIX Symposium on Internet Technologies and Systems,
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H. Kim, V. S. Pai and S. Rixner,"Increasing Web Server Throughput with Network Interface Data Caching," in International Conference on Architectural Support for Programming Languages and Operating Systems (A,, pp. 239-250.
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C. J. Hughes, V. S. Pai, P. Ranganathan and S. V. Adve, "Rsim: Simulating Shared-Memory Multiprocessors with ILP Processors," IEEE Computer, vol. 35, no. 2, pp. 40-49, 2002.
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V. S. Pai, "Performance Evolution," Computer Performance Evaluation Workshop, 2001.
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V. S. Pai and S. V. Adve,"Comparing and Combining
Read Miss Clustering and Software Prefetching," in International Symposium on Parallel Architectures and Compilation Techniques (PACT),, pp. 292-303.
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V. S. Pai, "Exploiting Instruction-Level Parallelism for Memory System Performance," Ph.D. Thesis, 2000.
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V. S. Pai and S. V. Adve, "Code Transformations to Improve Memory Parallelism," Journal of Instruction-Level Parallelism, vol. 2, 2000.
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V. S. Pai and S. V. Adve,"Code Transformations to Improve Memory Parallelism," in IEEE/ACM International Symposium on Microarchitecture (MICRO),, pp. 147-155.
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S. V. Adve, V. S. Pai and P. Ranganathan, "Recent Advances in Memory Consistency
Models for Hardware Shared Memory Systems," Proceedings of the IEEE, vol. 87, no. 3, pp. 445-455, 1999.
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V. S. Pai, P. Ranganathan, H. Abdel-Shafi and S. V. Adve, "The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors," IEEE Transactions on Computers, vol. 48, no. 2, pp. 218-226, 1999.
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M. Durbhakula, V. S. Pai and S. V. Adve,"Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors," in International Symposium on High Performance Computer Architecture (HPCA),, pp. 23-32.
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D. J. Sorin, V. S. Pai, S. V. Adve, M. K. Vernon and D. A. Wood,"Analytic Evaluation of Shared-Memory Systems with ILP Processors," in International Symposium on Computer Architecture (ISCA),, pp. 380-391.
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D. J. Sorin, M. K. Vernon, V. S. Pai, S. V. Adve and D. A. Wood, "A Customized MVA Model for ILP Multiprocessors," University of Wisconsin-Madison Computer Sciences Technical Report, no. 1369, 1998.
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V. S. Pai, P. Ranganathan and S. V. Adve, "RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors," IEEE Technical Committee on Computer Architecture Newsletter, 1997.
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V. S. Pai, P. Ranganathan and S. V. Adve, "RSIM Reference Manual: Version 1.0," Rice University ECE Technical Report, no. 9705, 1997.
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P. Ranganathan, V. S. Pai, H. Abdel-Shafi and S. V. Adve,"The Interaction of Software Prefetching with ILP Processors in Shared-Memory Systems," in International Symposium on Computer Architecture (ISCA),, pp. 144-156.
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P. Ranganathan, V. S. Pai and S. V. Adve,"Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models," in ACM Symposium on Parallel Algorithms and Architectures (SPAA),, pp. 199-210.
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V. S. Pai, "The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology," Masters Thesis, 1997.
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V. S. Pai, P. Ranganathan and S. V. Adve,"The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology," in International Symposium on High Performance Computer Architecture (HPCA),, pp. 72-83.
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V. S. Pai, P. Ranganathan, S. V. Adve and T. Harton,"An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors," in International Conference on Architectural Support for Programming Languages and Operating Systems (A,, pp. 12-23.
V. S. Pai, S. Rixner and H. Kim, "Isolating the Performance Impacts of Network Interface Cards through Microbenchmarks," Rice University ECE Technical Report, no. EE0401, 2004.
K. Skadron, M. Martonosi, D. August, M. Hill, D. Lilja and V. S. Pai, "Challenges in Computer Architecture Evaluation," IEEE Computer, vol. 36, no. 8, pp. 30-36, 2003.
H. Kim, V. S. Pai and S. Rixner,"Exploiting Task-Level Concurrency in a Programmable Network Interface," in ACM SIGPLAN Symposium on Principles and Practices of Parallel Programming (PPoPP),
V. S. Pai, A. Cox, V. S. Pai and W. Zwaenepoel,"A Flexible and Efficient Application Programming Interface (API) for a Customizable Proxy Cache," in USENIX Symposium on Internet Technologies and Systems,
H. Kim, V. S. Pai and S. Rixner,"Increasing Web Server Throughput with Network Interface Data Caching," in International Conference on Architectural Support for Programming Languages and Operating Systems (A,, pp. 239-250.
C. J. Hughes, V. S. Pai, P. Ranganathan and S. V. Adve, "Rsim: Simulating Shared-Memory Multiprocessors with ILP Processors," IEEE Computer, vol. 35, no. 2, pp. 40-49, 2002.
V. S. Pai, "Performance Evolution," Computer Performance Evaluation Workshop, 2001.
V. S. Pai and S. V. Adve,"Comparing and Combining Read Miss Clustering and Software Prefetching," in International Symposium on Parallel Architectures and Compilation Techniques (PACT),, pp. 292-303.
V. S. Pai, "Exploiting Instruction-Level Parallelism for Memory System Performance," Ph.D. Thesis, 2000.
V. S. Pai and S. V. Adve, "Code Transformations to Improve Memory Parallelism," Journal of Instruction-Level Parallelism, vol. 2, 2000.
V. S. Pai and S. V. Adve,"Code Transformations to Improve Memory Parallelism," in IEEE/ACM International Symposium on Microarchitecture (MICRO),, pp. 147-155.
S. V. Adve, V. S. Pai and P. Ranganathan, "Recent Advances in Memory Consistency Models for Hardware Shared Memory Systems," Proceedings of the IEEE, vol. 87, no. 3, pp. 445-455, 1999.
V. S. Pai, P. Ranganathan, H. Abdel-Shafi and S. V. Adve, "The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors," IEEE Transactions on Computers, vol. 48, no. 2, pp. 218-226, 1999.
M. Durbhakula, V. S. Pai and S. V. Adve,"Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors," in International Symposium on High Performance Computer Architecture (HPCA),, pp. 23-32.
D. J. Sorin, V. S. Pai, S. V. Adve, M. K. Vernon and D. A. Wood,"Analytic Evaluation of Shared-Memory Systems with ILP Processors," in International Symposium on Computer Architecture (ISCA),, pp. 380-391.
D. J. Sorin, M. K. Vernon, V. S. Pai, S. V. Adve and D. A. Wood, "A Customized MVA Model for ILP Multiprocessors," University of Wisconsin-Madison Computer Sciences Technical Report, no. 1369, 1998.
V. S. Pai, P. Ranganathan and S. V. Adve, "RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors," IEEE Technical Committee on Computer Architecture Newsletter, 1997.
V. S. Pai, P. Ranganathan and S. V. Adve, "RSIM Reference Manual: Version 1.0," Rice University ECE Technical Report, no. 9705, 1997.
P. Ranganathan, V. S. Pai, H. Abdel-Shafi and S. V. Adve,"The Interaction of Software Prefetching with ILP Processors in Shared-Memory Systems," in International Symposium on Computer Architecture (ISCA),, pp. 144-156.
P. Ranganathan, V. S. Pai and S. V. Adve,"Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models," in ACM Symposium on Parallel Algorithms and Architectures (SPAA),, pp. 199-210.
The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation MethodologyV. S. Pai, "The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology," Masters Thesis, 1997.
The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation MethodologyV. S. Pai, P. Ranganathan and S. V. Adve,"The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology," in International Symposium on High Performance Computer Architecture (HPCA),, pp. 72-83.
V. S. Pai, P. Ranganathan, S. V. Adve and T. Harton,"An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors," in International Conference on Architectural Support for Programming Languages and Operating Systems (A,, pp. 12-23.