Browse the entire archive

Advanced Search

My Account

Statistics

View Statistics

Browsing ECE Publications by Author "Karkooti, Marjan"

Browse this collection by:

Date | Authors | Titles | Subjects | Type

Now showing items 1-12 of 12

Configurable LDPC Decoder Architecture for Regular and Irregular Codes

M. Karkooti, P. Radosavljevic and J. R. Cavallaro, "Configurable LDPC Decoder Architecture for Regular and Irregular Codes," Springer Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, vol. 53, no. 1-2, pp. 73-88, 2008.
Distributed Decoding in Cooperative Communications

M. Karkooti and J. R. Cavallaro,"Distributed Decoding in Cooperative Communications," in 41st Asilomar Conference on Signals, Systems and Computers, 2007, pp. 824-828.
VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes

Y. Sun, M. Karkooti and J. R. Cavallaro,"VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes," in IEEE International Symposium on Circuits and Systems (ISCAS), 2007, pp. 2104-2107.
HIGH THROUGHPUT, PARALLEL, SCALABLE LDPC ENCODER/DECODER ARCHITECTURE FOR OFDM SYSTEMS

Y. Sun, M. Karkooti and J. R. Cavallaro,"HIGH THROUGHPUT, PARALLEL, SCALABLE LDPC ENCODER/DECODER ARCHITECTURE FOR OFDM SYSTEMS," in IEEE Dallas Circuits and Systems Workshop on Design, Applications, Integration and Software, 2006, pp. 39-42.
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation

M. Karkooti, P. Radosavljevic and J. R. Cavallaro,"Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation," in IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP),
Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis between Decoding Throughput and Area

P. Radosavljevic, A. de Baynast, M. Karkooti and J. R. Cavallaro,"Multi-Rate High-Throughput LDPC Decoder: Tradeoff Analysis between Decoding Throughput and Area," in IEEE International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC),
High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity Check Matrices

P. Radosavljevic, A. de Baynast, M. Karkooti and J. R. Cavallaro,"High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity Check Matrices," in European Signal Processing Conference,
High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity-Check Matrices

P. Radosavljevic, A. de Baynast, M. Karkooti and J. R. Cavallaro,"High-Throughput Multi-rate LDPC Decoder based on Architecture-Oriented Parity-Check Matrices," in European Signal Processing Conference,
FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm

M. Karkooti, J. R. Cavallaro and C. Dick,"FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm," in Asilomar Conference on Signals, Systems, and Computers,
FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm

M. Karkooti, J. R. Cavallaro and C. Dick,"FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm," in Asilomar Conference on Signals, Systems, and Computers,, pp. 1625 - 1629.
Semi-Parallel Architectures For Real-time LDPC Coding

M. Karkooti, "Semi-Parallel Architectures For Real-time LDPC Coding," Masters Thesis, 2004.
Semi-parallel Reconfigurable Architectures for Real-time LDPC Decoding

M. Karkooti and J. R. Cavallaro,"Semi-parallel Reconfigurable Architectures for Real-time LDPC Decoding," in International Conference on Information Technology(ITCC),, pp. 579-585.