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C. J. Hughes, V. S. Pai, P. Ranganathan and S. V. Adve, "Rsim: Simulating Shared-Memory Multiprocessors with ILP Processors," IEEE Computer, vol. 35, no. 2, pp. 40-49, 2002.
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V. S. Pai and S. V. Adve,"Comparing and Combining
Read Miss Clustering and Software Prefetching," in International Symposium on Parallel Architectures and Compilation Techniques (PACT),, pp. 292-303.
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V. S. Pai and S. V. Adve, "Code Transformations to Improve Memory Parallelism," Journal of Instruction-Level Parallelism, vol. 2, 2000.
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V. S. Pai and S. V. Adve,"Code Transformations to Improve Memory Parallelism," in IEEE/ACM International Symposium on Microarchitecture (MICRO),, pp. 147-155.
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S. V. Adve, V. S. Pai and P. Ranganathan, "Recent Advances in Memory Consistency
Models for Hardware Shared Memory Systems," Proceedings of the IEEE, vol. 87, no. 3, pp. 445-455, 1999.
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V. S. Pai, P. Ranganathan, H. Abdel-Shafi and S. V. Adve, "The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors," IEEE Transactions on Computers, vol. 48, no. 2, pp. 218-226, 1999.
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M. Durbhakula, V. S. Pai and S. V. Adve,"Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors," in International Symposium on High Performance Computer Architecture (HPCA),, pp. 23-32.
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D. J. Sorin, V. S. Pai, S. V. Adve, M. K. Vernon and D. A. Wood,"Analytic Evaluation of Shared-Memory Systems with ILP Processors," in International Symposium on Computer Architecture (ISCA),, pp. 380-391.
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D. J. Sorin, M. K. Vernon, V. S. Pai, S. V. Adve and D. A. Wood, "A Customized MVA Model for ILP Multiprocessors," University of Wisconsin-Madison Computer Sciences Technical Report, no. 1369, 1998.
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V. S. Pai, P. Ranganathan and S. V. Adve, "RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors," IEEE Technical Committee on Computer Architecture Newsletter, 1997.
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V. S. Pai, P. Ranganathan and S. V. Adve, "RSIM Reference Manual: Version 1.0," Rice University ECE Technical Report, no. 9705, 1997.
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P. Ranganathan, V. S. Pai and S. V. Adve,"Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models," in ACM Symposium on Parallel Algorithms and Architectures (SPAA),, pp. 199-210.
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P. Ranganathan, V. S. Pai, H. Abdel-Shafi and S. V. Adve,"The Interaction of Software Prefetching with ILP Processors in Shared-Memory Systems," in International Symposium on Computer Architecture (ISCA),, pp. 144-156.
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V. S. Pai, P. Ranganathan and S. V. Adve,"The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology," in International Symposium on High Performance Computer Architecture (HPCA),, pp. 72-83.
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V. S. Pai, P. Ranganathan, S. V. Adve and T. Harton,"An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors," in International Conference on Architectural Support for Programming Languages and Operating Systems (A,, pp. 12-23.
C. J. Hughes, V. S. Pai, P. Ranganathan and S. V. Adve, "Rsim: Simulating Shared-Memory Multiprocessors with ILP Processors," IEEE Computer, vol. 35, no. 2, pp. 40-49, 2002.
V. S. Pai and S. V. Adve,"Comparing and Combining Read Miss Clustering and Software Prefetching," in International Symposium on Parallel Architectures and Compilation Techniques (PACT),, pp. 292-303.
V. S. Pai and S. V. Adve, "Code Transformations to Improve Memory Parallelism," Journal of Instruction-Level Parallelism, vol. 2, 2000.
V. S. Pai and S. V. Adve,"Code Transformations to Improve Memory Parallelism," in IEEE/ACM International Symposium on Microarchitecture (MICRO),, pp. 147-155.
S. V. Adve, V. S. Pai and P. Ranganathan, "Recent Advances in Memory Consistency Models for Hardware Shared Memory Systems," Proceedings of the IEEE, vol. 87, no. 3, pp. 445-455, 1999.
V. S. Pai, P. Ranganathan, H. Abdel-Shafi and S. V. Adve, "The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors," IEEE Transactions on Computers, vol. 48, no. 2, pp. 218-226, 1999.
M. Durbhakula, V. S. Pai and S. V. Adve,"Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors," in International Symposium on High Performance Computer Architecture (HPCA),, pp. 23-32.
D. J. Sorin, V. S. Pai, S. V. Adve, M. K. Vernon and D. A. Wood,"Analytic Evaluation of Shared-Memory Systems with ILP Processors," in International Symposium on Computer Architecture (ISCA),, pp. 380-391.
D. J. Sorin, M. K. Vernon, V. S. Pai, S. V. Adve and D. A. Wood, "A Customized MVA Model for ILP Multiprocessors," University of Wisconsin-Madison Computer Sciences Technical Report, no. 1369, 1998.
V. S. Pai, P. Ranganathan and S. V. Adve, "RSIM: An Execution-Driven Simulator for ILP-Based Shared-Memory Multiprocessors and Uniprocessors," IEEE Technical Committee on Computer Architecture Newsletter, 1997.
V. S. Pai, P. Ranganathan and S. V. Adve, "RSIM Reference Manual: Version 1.0," Rice University ECE Technical Report, no. 9705, 1997.
P. Ranganathan, V. S. Pai and S. V. Adve,"Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models," in ACM Symposium on Parallel Algorithms and Architectures (SPAA),, pp. 199-210.
P. Ranganathan, V. S. Pai, H. Abdel-Shafi and S. V. Adve,"The Interaction of Software Prefetching with ILP Processors in Shared-Memory Systems," in International Symposium on Computer Architecture (ISCA),, pp. 144-156.
The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation MethodologyV. S. Pai, P. Ranganathan and S. V. Adve,"The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology," in International Symposium on High Performance Computer Architecture (HPCA),, pp. 72-83.
V. S. Pai, P. Ranganathan, S. V. Adve and T. Harton,"An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors," in International Conference on Architectural Support for Programming Languages and Operating Systems (A,, pp. 12-23.