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Browsing by Author "Rajagopal, Sridhar"

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Now showing items 1-22 of 22

Arithmetic Acceleration Techniques for Wireless Communication Receivers

Das, Suman; Rajagopal, Sridhar; Sengupta, Chaitali; Cavallaro, Joseph R. (1999-10-20)
Baseband architecture design for future wireless base-station receivers

Rajagopal, Sridhar (2000)
Baseband Architecture Design for Future Wireless Base-Station Receivers

Rajagopal, Sridhar (2000-05-20)
A bit-streaming pipelined multiuser detector for wireless communications

Rajagopal, Sridhar; Cavallaro, Joseph R. (2001-05-20)
Communication Processors

Rajagopal, Sridhar; Cavallaro, Joseph R. (Wiley, 2005-07-01)
Data-parallel digital signal processors: Algorithm mapping, architecture scaling and workload adaptation

Rajagopal, Sridhar (2004)
Data-parallel Digital Signal Processors: Algorithm Mapping, Architecture Scaling and Workload Adaptation

Rajagopal, Sridhar (2004-05-01)
Design space exploration for real-time embedded stream processors

Rajagopal, Sridhar; Cavallaro, Joseph R.; Rixner, Scott (2004-07-01)
DSP architectural considerations for optimal baseband processing

Rajagopal, Sridhar; Rixner, Scott; Cavallaro, Joseph R.; Aazhang, Behnaam (2002-08-20)
Efficient VLSI Architectures for Baseband Signal Processing for Wireless Base-Station Receivers

Rajagopal, Sridhar; Bhashyam, Srikrishna; Cavallaro, Joseph R.; Aazhang, Behnaam (2000-07-20)
Efficient VLSI architectures for multiuser channel estimation in wireless base-station receivers

Rajagopal, Sridhar; Bhashyam, Srikrishna; Cavallaro, Joseph R.; Aazhang, Behnaam (Kluwer Academic Pubishers, 2002-06-20)
Implementation of Channel Estimation and Multiuser Detection Algorithms for W-CDMA on Digital Signal Processors

Rajagopal, Sridhar; Xu, Gang; Cavallaro, Joseph R. (1999-08-20)
Improving power efficiency in stream processors through dynamic cluster reconfiguration

Rajagopal, Sridhar; Rixner, Scott; Cavallaro, Joseph R. (2004-12-01)
On-line Arithmetic for Detection in Digital Communication Receivers

Rajagopal, Sridhar; Cavallaro, Joseph R. (2001-06-20)
A programmable baseband processor design for software defined radios

Rajagopal, Sridhar; Rixner, Scott; Cavallaro, Joseph R. (IEEE, 2002-08-20)
Real-Time Algorithms and Architectures for Multiuser Channel Estimation and Detection in Wireless Base-Station Receivers

Rajagopal, Sridhar; Bhashyam, Srikrishna; Cavallaro, Joseph R.; Aazhang, Behnaam (IEEE, 2002-07-20)
Real-Time DSP Multiprocessor Implementation for Future Wireless Base-Station Receivers

Jones, Bryan Allen; Rajagopal, Sridhar; Cavallaro, Joseph R. (2000-08-20)
Reconfigurable stream processors for wireless base-stations

Rajagopal, Sridhar; Rixner, Scott; Cavallaro, Joseph R. (2003-10-20)
Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs

Rajagopal, Sridhar; Jones, Bryan Allen; Cavallaro, Joseph R. (2000-10-20)
Truncated on-line arithmetic with applications to communication systems

Rajagopal, Sridhar; Cavallaro, Joseph R. (2006-09-01)
Truncated Online Arithmetic with Applications to Communication Systems

Rajagopal, Sridhar; Cavallaro, Joseph R. (IEEE, 2006-10)
VLSI implementation of the multistage detector for next generation wideband CDMA receivers

Xu, Gang; Rajagopal, Sridhar; Cavallaro, Joseph R.; Aazhang, Behnaam (Kluwer Academic Publishers, 2002-03-20)